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Espressif Systems /ESP32-S2 /USB_WRAP /OTG_CONF

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Interpret as OTG_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SRP_SESSEND_OVERRIDE)SRP_SESSEND_OVERRIDE 0 (SRP_SESSEND_VALUE)SRP_SESSEND_VALUE 0 (PHY_SEL)PHY_SEL 0 (DFIFO_FORCE_PD)DFIFO_FORCE_PD 0 (DBNCE_FLTR_BYPASS)DBNCE_FLTR_BYPASS 0 (EXCHG_PINS_OVERRIDE)EXCHG_PINS_OVERRIDE 0 (EXCHG_PINS)EXCHG_PINS 0VREFH 0VREFL 0 (VREF_OVERRIDE)VREF_OVERRIDE 0 (PAD_PULL_OVERRIDE)PAD_PULL_OVERRIDE 0 (DP_PULLUP)DP_PULLUP 0 (DP_PULLDOWN)DP_PULLDOWN 0 (DM_PULLUP)DM_PULLUP 0 (DM_PULLDOWN)DM_PULLDOWN 0 (PULLUP_VALUE)PULLUP_VALUE 0 (USB_PAD_ENABLE)USB_PAD_ENABLE 0 (AHB_CLK_FORCE_ON)AHB_CLK_FORCE_ON 0 (PHY_CLK_FORCE_ON)PHY_CLK_FORCE_ON 0 (PHY_TX_EDGE_SEL)PHY_TX_EDGE_SEL 0 (DFIFO_FORCE_PU)DFIFO_FORCE_PU 0 (CLK_EN)CLK_EN

Description

USB OTG Wrapper Configure Register

Fields

SRP_SESSEND_OVERRIDE

This bit is used to enable the software over-ride of srp session end signal. 1’b0: the signal is controlled by the chip input. 1’b1: the signal is controlled by the software.
SRP_SESSEND_VALUE

Software over-ride value of srp session end signal.
PHY_SEL

Select internal external PHY. 1’b0: Select internal PHY. 1’b1: Select external PHY.
DFIFO_FORCE_PD

Force the dfifo to go into low power mode. The data in dfifo will not lost.
DBNCE_FLTR_BYPASS

Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
EXCHG_PINS_OVERRIDE

Enable software controlle USB D+ D- exchange
EXCHG_PINS

USB D+ D- exchange. 1’b0: don’t change. 1’b1: exchange D+ D-
VREFH

Control single-end input high threshold,1.76V to 2V, step 80mV
VREFL

Control single-end input low threshold,0.8V to 1.04V, step 80mV
VREF_OVERRIDE

Enable software controlle input threshold
PAD_PULL_OVERRIDE

Enable software controlle USB D+ D- pullup pulldown
DP_PULLUP

Controlle USB D+ pullup
DP_PULLDOWN

Controlle USB D+ pulldown
DM_PULLUP

Controlle USB D+ pullup
DM_PULLDOWN

Controlle USB D+ pulldown
PULLUP_VALUE

Controlle pullup value. 1’b0: typical value is 2.4K. 1’b1: typical value is 1.2K.
USB_PAD_ENABLE

Enable USB pad function
AHB_CLK_FORCE_ON

Force ahb clock always on
PHY_CLK_FORCE_ON

Force phy clock always on
PHY_TX_EDGE_SEL

Select phy tx signal output clock edge. 1’b0: negedge. 1’b1: posedge.
DFIFO_FORCE_PU

Disable the dfifo to go into low power mode. The data in dfifo will not lost.
CLK_EN

Disable auto clock gating of CSR registers

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd